Job Title: Optical Engineer, Design Analysis 
Duration: 24 Months
Location: Redmond WA
 
Job Description:

• We are looking for an Optical Engineer with passion for new technology development to join our team, whose mission is to deliver beyond state-of-the-art display system technologies for consumer near to eye displays at our research and development facilities.
• We are looking for a candidate with experience in novel-integrated photonics device design and metrology either as part of their PhD or industry experience.

 
About the Team:

• R&D team focused on cutting-edge near-to-eye display systems.
• Multidisciplinary collaboration with engineers, researchers, and program managers.
• Drives innovation in integrated photonics and display technology.

 
Key Projects/Day-to-Day: Responsibilities:

• Design, simulate, and optimize PICs and photonic devices.
• Prepare fabrication-ready layouts and ensure compliance with foundry PDKs.
• Analyze and improve designs through parametric studies.
• Coordinate the design-to-fabrication pipeline with cross-functional teams and external partners.
• Collaborate with leadership and researchers to align designs with program goals.

 
How will progress be evaluated? What does success look like for this assignment

• Successful design and tapeout of PICs.
• Quality and innovation in device simulation, layout, and fabrication.
• Effective collaboration and alignment with program goals.
• Ability to optimize designs for performance and manufacturability.

 
What makes this role attractive to top talent, and what unique value does it offer to the ideal candidate?

• Opportunity to work on cutting-edge photonics for next-generation display technology.
• Collaborate with top experts in a highly innovative R&D environment.
• Direct impact on product development and technology advancement.

 
Purpose/Size of this team & where does this position fit within the team?

• Key technical contributor in the R&D team, collaborating with leadership, TPMs, and researchers.
• Drives PIC design and fabrication efforts, bridging technical and program objectives.

 
Certain project that team is working on / what products are they supporting:

• Developing advanced photonic integrated circuits for next-gen near-to-eye display systems.
• Integrating active devices and optimizing for fabrication constraints.
• Improving system-level performance and yield through design analysis and modeling.

 
Must-Have Skills:

1. PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
2. Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
3. PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.

 
Nice-to-Have Skills:

1. Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.

1. Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
2. Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.

 
Minimum Years of Experience:

• 5-7 years of experience

 
Degrees/Certifications Required:

• MS or Ph.D. degree (preferred) in Electrical Engineering, Optical Sciences, Physics, or a closely related field.

 
Optical Engineer, PIC Design & Analysis Responsibilities:

• Collaborate with leadership, TPMs, and researchers on Photonic Integrated Circuit (PIC) designs aligned with program priorities.
• Design and develop full PICs, from component blocks to full circuits, focusing on active device integration.
• Generate and verify fabrication-ready layout files compliant with foundry PDKs for external fabrication.
• Conduct systematic design analysis, including optimization and parametric studies, to inform design decisions.
• Support the full design-to-fabrication workflow, from concept through tapeout, with cross-functional teams and external partners.

 
MINIMUM QUALIFICATIONS

• MS or PhD degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
• 3+ years of hands-on experience in the design, simulation, and layout of photonic integrated circuits (PICs), for visible or IR wavelengths on Si / SiN / LiNbO / BTO platforms.
• 3+ years of experience with photonic device simulation and electromagnetic modeling tools for component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
• 2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
• 2+ years of experience with scientific programming languages such as Python or MATLAB for design automation, analysis, and scripting.
• 1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, with fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).

 
PREFERRED QUALIFICATIONS

• 3+ years experience in active photonic integrated circuit (PIC) design, fabrication and validation for visible wavelengths on LiNbO / BTO platforms.
• 3+ years of experience in design space exploration and sensitivity analysis for photonic circuits, including statistical performance and yield modeling.
• 3+ years of experience in one or more photonic simulation tool suites such as Lumerical, Synopsys, COMSOL, or equivalent.
• 2+ years of experience with photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
• 2+ years of experience in photonic device characterization and test, including optical and electro-optic measurements.
• 1+ years experience with fiber optics, free space optics, PIC packaging, and device characterization.
• 1+ years experience with semiconductor fab processes and understanding of fabrication-induced performance limitations, including optical losses, sidewall roughness, and process variability.
• Demonstrated ability to incorporate fab constraints into PIC design (e.g., minimum feature sizes, bend radii optimization, tapering strategies, and layout considerations to mitigate scattering and coupling losses).

 
 
At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $ 75.00/hr.