Role: Signal Integrity/ Power Engineer
Type: Direct hire (Full-time)
Location: Dallas - Fort-Worth, TX / Austin, TX / Silicon Valley, CA

Scope:

• High-Speed Interconnect & SerDes Design: Lead the end-to-end design, development, and signal integrity (SI) testing for high-speed interconnects—including PCBAs, PCBs, connectors, and cables—specifically for large-scale tray and rack-level products. You will design and analyze cutting-edge high-speed links, such as 224G SerDes, PCIe, and also working on DDR, and other high-speed clocks and interfaces.
• End-to-End SI Analysis & Simulation: Perform comprehensive pre- and post-layout SI/PI simulations using industry-standard tools (HFSS, MATLAB, ADS, and Cadence Sigrity). You will be responsible for driving actionable feedback on PCBAs, including stackup updates and approval, connectors and cables, routing, vias, and return paths to optimize performance across the entire signal path.
• Cross-Functional Collaboration & Vendor Management: Act as a central technical point of contact, working cross-functionally with CAD, EE, Thermal, Mechanical, and Manufacturing teams. You will collaborate closely with the CAD team for layout execution and partner with external ASIC vendors, memory vendors, and PCB suppliers to close technical constraints and ensure design feasibility. You will be proposing and closing on PCB stack-ups with the fab vendors to deliver PCBA solution that meets SI, Power, Mechanical and DFM requirements.
• Lab Validation, Testing, & Debug: Participate in hands-on lab activities, leading hardware qualification and validation for high-speed interconnects. Use VNAs, high-bandwidth oscilloscopes, and high-speed probes to perform debugging as needed, translating real-world lab findings into tangible design improvements.
• System-Level Design for Scalability: Operate in a fast-paced environment to ensure all designs for large rack systems are reliable, manufacturable at scale (DFM/DFA), and strictly compliant with system specifications. You will bridge the gap between initial simulation/design and final platform validation.

What We’re Looking For:

• High-Speed Interface Expertise: Expertise in the design, development, and testing of SerDes architectures and high-speed interconnects (PCBAs, PCBs, connectors, cables) for tray and rack-level systems. Ideally 224 gig SerDes experience (also open to 100gig, 50 gig or 25 gig SerDes experience).
• Board Level Design Expertise: Strong PCB design skills with a preference for candidates from high-scale networking/compute firms (e.g., Arista, Juniper, Cisco, Dell, HP). Open to chip-level talent with relevant board-level experience.
• Advanced Signal & Power Integrity Tools: Proficiency in pre- and post-layout Signal Integrity (SI) and Power Integrity (PI) using tools such as HFSS, MATLAB, ADS, Cadence Allegro, and HyperLynx. Capable to perform power analysis using Cadence Sigrity.
• Lab Validation & Debugging: Hands-on experience with DDR and PCI interfaces. Required proficiency with lab equipment such as VNAs (Vector Network Analyzers) and oscilloscopes to qualify designs.
• Specialized Electrical Domains: Technical depth in Point of Load (PoL) switching supplies, Battery management, and RF Design (both 20GHz), along with Static Timing and Tolerance Analysis.
• Cross-Functional Leadership: Proven ability to lead engineering teams and collaborate with CAD, Thermal, Mechanical, and Manufacturing functions while managing technical relationships with ASIC, memory, connector, cable and PCB vendors.

End to end simulation experience strongly preferred. 
 


At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $ 200000.00/Yearly.