Job Title: Silicon DD Engineer IV
Duration: 12 Months
Location: Redmond, WA or Sunnyvale, CA
Role:

• Develop and test RTL modules on AMD/Xilinx FPGA devices (required) and ASIC targets (preferred)
• Develop and maintain build/simulation scripts
• Write test cases using Python to validate our design
• Create software interfaces from our FPGA-based systems to Windows and Linux systems software at the HAL layer
• Collaborate in a team environment across multiple engineering disciplines and with researchers

Must-Have Skills:

• Experience in System Verilog and VHDL is acceptable
• Proficient or expert in Xilinx/FPGAs
• FPGA verification (Simulation verification)

Nice-to-have Skills:

• Python scripting for test use cases
• ASIC development familiarity
• Common video and camera standards (DSI and CSI)

Skills Minimum:

• 5+ years of FPGA design experience using Verilog, SystemVerilog
• 5+ years of experience in AMD/Xilinx FPGA design (Versal and Kintex/Virtex UltraScale+ desired, 7-series minimum)
• Experience using industry standard Xilinx Vivado to bring up initial system, integrate peripheral components, and test and debug design
• Programming experience in one or more scripting languages: Python, tcl, shell scripts, or equivalent EDA tool scripting languages

Preferred:

• 10+ years of experience in FPGA design and development
• Experience with RTL to GDS flows on modern processes like TSMC N7
• Experience with serial interfaces like SPI, I2C and video/camera interfaces like MIPI DSI/CSI
• Proven track record of successfully deploying FPGA solutions across production systems or research prototypes
• Programming experience in C and/or C++
• Experience developing accompanying firmware to exercise and drive FPGA prototypes

Education:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience

What are the top non-negotiable skill sets required for this role:

• Experience in RTL coding, synthesis and/or SoC Integration
• Experience in digital design µArchitecture
• Familiarity with Verilog, systemVerilog coding

Duties:

• Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
• IPs integration
• Understand Design for Verification concepts
• Drive the top-level µArchitecture definition and develop the necessary RTL
• Drive the chip-level integration, verification plan development and verification
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
• Support the test program development, chip validation and chip life until production maturity
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis, verification and improvement
• Contribute to ASIC digital architecture, design and verification

Must Have:

• 4+ years of experience as a Digital Design Engineer and/or a Chip Lead
• Experience in RTL coding, synthesis and/or SoC Integration
• Experience in digital design µArchitecture

Wish List/ Nice to Have:

• Experience using High Speed interfaces like PCIe, USB, MIPI
• FPGA design

Education:

• Must Have: Bachelor’s degree in electrical/computer engineering or computer science
• Master's Degree preferred but not required

Key Projects/Day-to-Day Responsibilities:        

• Project they would work on is FPGA (Field Programmable Gate Array) device, working on prototyping, custom cameras. New project coming next year.

Purpose/Size of this team & where does this position fit within the team:

• 5 People

What makes this role interesting:

• They get a chance to work cutting edge, designs, FPGA and ML tech, beyond state of the art.

 

 


At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $90.00/hr.