Job Title: Design Verification Engineer (Mixed-Signal / High-Speed IP)
Location: San Diego, CA (Onsite – 100%)
Duration : 12 Months
Workdays: Monday to Friday
Shift Time: 8:30am to 5:00pm

Job Summary

Join Design Verification team to work on high-speed mixed-signal IPs such as PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, and Sensors.
You will be involved in the complete verification lifecycle—from system-level concept to tape-out and post-silicon validation—for cutting-edge products in 5G, AI/ML, compute, IoT, and automotive domains.

Key Responsibilities

• Define pre-silicon and post-silicon test plans based on design specifications and industry standards.
• Architect and develop testbenches using SystemVerilog UVM methodology.
• Perform mixed-signal verification, including analog/digital co-simulation.
• Implement low-power verification, formal verification, and gate-level simulations.
• Write SystemVerilog Assertions (SVA), develop test cases, and build coverage models.
• Debug issues and drive functional and code coverage closure.
• Collaborate with:
• Digital Design teams
• Analog Circuit Design teams
• Modeling teams
• Controller/Subsystem teams
• SoC Integration teams
• Support PHY-level verification, subsystem integration, and post-silicon validation.

(Nice to have) Develop Verification IP (VIP) from scratch for SerDes/Controller PHY.

Experience Required: 5+ Years
Education: Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field

Required Skills

• Strong expertise in SystemVerilog and UVM methodology
• Experience with ASIC verification tools such as:
• VCS
• Xcelium / NCSim
• ModelSim / Questa
• VC Formal, JasperGold, 0-In
• Solid understanding of high-speed interface protocols:
• PCIe
• USB (2.0/3.x/4)
• MIPI (CSI/DSI)
• UFS
• HDMI
• DDR / LPDDR PHY
• Strong experience in SystemVerilog Assertions (SVA) and debugging
• Good problem-solving and analytical skills

Preferred Qualifications

• Experience in low-power verification (UPF-based simulations)
• Experience in formal verification and gate-level simulations
• Knowledge of scripting languages such as Python or Perl
• Experience in mixed-signal IP verification (PLL, ADC, DAC, Sensors, etc.)
• Exposure to protocols like CXL, C2C, D2D

 
 
At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $ 81.00/hr.