Job Title: ASIC Power Engineer 
Location: Sunnyvale CA - Hybrid
Duration: 6 months, potential extension

Job Description:
Role: ASIC Power Engineer
Duties:
ASIC Power Engineer to perform power analysis and optimizations in ASIC for Client’s AR/VR products. Areas of interest include Machine Learning. Primary languages are Python, Tcl, and SystemVerilog.
 
Must-Have Skills

1. Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
2. Should know how to use Python, Perl (or similar) scripting and data post-processing tools.
3. Experience in low-power design, tools, and methodologies, including power intent UPF specifications.
   Silicon power characterization.

 
Nice-to-have Skills

1. Some power profiling experience at IP/SoC level.
2. Experience with silicon power characterization.
3. Experience with data analytics and visualization.

 
Years of Experience:

• 10+ years of experience as an ASIC Power Engineer or CAD Engineer/Physical Design Engineer.

 
 
Responsibilities:

• Perform PPA optimization with Fusion Compiler.
• Perform RTL and netlist-level power analysis.
• Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
• Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
• Implement some blocks at RTL and UPF.
• Ability to document and communicate clearly.

 
Minimum Qualifications:

• 10+ years of experience as an ASIC Power Engineer or CAD Engineer/Physical Design Engineer.
• Experience with power estimation tools and synthesis, some physical design.
• Knowledge of power trade-offs in design and backend implementation.
• Hands-on experience in scripting and data analysis.
• BS in Electrical Engineering/Computer Science or equivalent experience.

 
Preferred Qualifications:

• Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
• Python, Perl (or similar) scripting and data post-processing tools.
• Excel (or Matlab) for model fitting, data visualization, and analysis.
• Experience in low-power design, tools, and methodologies, including power intent UPF specifications.
• Silicon power characterization.
• Some power profiling experience at IP/SoC level.

 
Key Projects/Day-to-Day Responsibilities:

• Perform PPA optimization with Fusion Compiler.
• Perform RTL and netlist-level power analysis.
• Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
• Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
• Implement some blocks at RTL and UPF.
• Ability to document and communicate clearly.

 
How will performance be measured?

• Based on rubrics, who handle 80% of their responsibilities.

 
What makes this role interesting?

• Designing the most advanced chips for AR/VR devices. Client owns the major market for VR devices. There are many opportunities to learn how to build chips for AR/VR products.

 
Value added or experience gained:

• CW will learn how to build a chip and also how to collaborate with software and hardware folks.

 
Degrees/Certifications Required:

• BS in Electrical Engineering/Computer Science or equivalent experience.

 
How many rounds of interviews? 2
Types of Interviews: Technical
Interview Duration: 30 minutes 
 
At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $ 100.00/hr.