Job Title: Silicon Physical Design Engineer III 
Duration: 12 Months (open to extension)
Location: Remote
 
What are the top non-negotiable skill sets required for this role?

• Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
• Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
• Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower

 
Duties:

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Power analysis based on netlist

 
Key Projects / Day-to-Day Responsibilities:

• Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
• Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge
• Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower

 
Duties:

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Power analysis based on netlist

 
Must-Have Skills:

1. Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower
2. Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge
3. Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies

Nice-to-have Skills:

1. MSEE/CS or equivalent experience

 
Years of Experience:

• 5 years of relevant physical design experience

 
Must Have:

• 5 years of relevant physical design experience
• Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in chip power analysis
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
• Experience with Python, TCL, Perl programming

 
Degrees/Certifications Required:

• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
• Master's Degree preferred but not required

 
Interview Process:

• How many rounds of interviews? 1 round
• Types of Interviews: Technical with coder pad
• Interview Duration: 1 hour

  
 
At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $ 90.00/hr.