Job Title: Silicon DD Engineer III 
Location: Remote (PST time zone preferred)
Duration: 6 months 
 
Job Description:
What are the top non-negotiable skill sets required for this role?

• Experience in RTL coding, synthesis and/or SoC Integration
• Experience in digital design Architecture
• Familiarity with Verilog, System Verilog coding

 
Duties:

• Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture, design and verification
• IPs integration
• Understand Design for Verification concepts
• Drive the top-level µArchitecture definition and develop the necessary RTL
• Drive the chip-level integration, verification plan development and verification
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
• Support the test program development, chip validation and chip life until production maturity
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis, verification and improvement
• Contribute to ASIC digital architecture, design and verification

 
Skills:
Must Have:

• 4+ years of experience as a Digital Design Engineer and/or a Chip Lead
• Experience in RTL coding, synthesis and/or SoC Integration
• Experience in digital design Architecture
• BS Electrical Engineering/Computer Science or equivalent experience
• Experience with UPF based simulation flow
• System Verilog OVM/UVM experience
• Tcl and Python (or similar) scripting experience
• Experience in SoC integration and ASIC architecture

 
Nice to Have:

• Experience in DFT/Testability requirement and test program definition
• Experience using High Speed interfaces like PCIe, USB, MIPI
• FPGA design
• Tensilica DSP, TIE, CNN, fixed point, floating point, Python
• Experience with Power Aware GLS flow
• MSEE/CS or equivalent experience

 
Years of Experience:

• 4+ years of experience as a Digital Design Engineer and/or a Chip Lead

 
Education:

• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
• Master's Degree: Preferred but not required

 
Story Behind the Need – Business Group & Key Projects:
Key Projects/Day-to-Day Responsibilities:

• Responsible for low power verification including both dynamic and static verification
• Write and augment existing testplans
• Implement testbench and scoreboards / checkers
• Implement test sequences as per plan and debug failures
• Achieve 100% functional, code, and power coverage
• Work closely with designers, micro architects & f/w to resolve issues
• Ability to communicate & articulate clearly progress / issues with project leads

 
Purpose/Size of this team & where does this position fit within the team?

• Team will be working on Everett V2

 
How will performance be measured?

• We have our own metrics that we will be meeting with the candidate on routinely and basing their work on

  

 


At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $100.00/hr.