Verification Engineer IV
Sunnyvale CA (Hybrid)
6 months 

Job Description
Summary:

• The main function of the Verification Engineer is to work with a group of researchers and engineers to own the electrical system level verification of Client's products. Working closely with researchers, architects, and designers in architecting methods of electrical verification for multiple state of the art systems. Using verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs.

 
Job Responsibilities:

• Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams
• Define and track detailed test plans for the different modules and top-level systems
• Define, architect, design, and drive implementation of scalable test infrastructure
• Create and enhance constraine-random verification environments using system Verilog and universal verification methodology (UVM) and track progress with coverage closure.
• Own execution, interpretation, and reporting of electrical system level verification work status and results
• Support system bring up and debug activities
• Clearly communicate test plans and results

 
Skills:

• Looking for a CW with hands on coding skill in SV/UVM
• Knowledge of definition of verification requirements
• Experience owning areas of product verification
• Knowledge of definition, architecture, design, and driving implementation of test automation
• Working knowledge of C#, Python, and LabVIEW
• Experience with firmware verification
• Experience in gate-level simulations and low power (UPF) verification is a plus
• Experience in silicon bring-up activities is advantageous

 
Education/Experience:

• Bachelors degree in Electrical Engineering, Computer Science or equivalent experience
• 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog

 
Must-Have Skills:

1. Hands on coding skill in SV/UVM. Strong System Verilog, debugging skills, experience owning areas of product verification
2. 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog
3. Working knowledge of C#, Python, and LabVIEW

 
Nice-to-have Skills:

• Experience in gate-level simulations and low power (UPF) verification is a plus

Years of Experience:      

• 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog

 
Degrees/Certifications Required:           

• Bachelors degree in Electrical Engineering, Computer Science or equivalent experience

   

 


At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position’s starting pay is: $80.00/hr.